PIC18C452T-E/L【PDF 57/279 页】IC MCU OTP 16KX16 A/D 44PLCC

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165

8197C–AVR–05/11

ATtiny261A/461A/861A

17.5

EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies

that the bit is cleared before writing to the SPMCSR Register.

17.6

Reading Fuse and Lock Bits from Software

It is possible for firmware to read device fuse and lock bits.

Note:

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unpro-

grammed, will be read as one.

17.6.1

Reading Lock Bits from Firmware

Lock bit values are returned in the destination register after an LPM instruction has been issued

within three CPU cycles after RFLB and SELFPRGEN bits have been set in SPMCSR. The

RFLB and SELFPRGEN bits automatically clear upon completion of reading the lock bits, or if no

LPM instruction is executed within three CPU cycles, or if no SPM instruction is executed within

four CPU cycles. When RFLB and SELFPRGEN are cleared LPM functions normally.

To read the lock bits, follow the below procedure:

Load the Z-pointer with 0x0001.

Set RFLB and SELFPRGEN bits in SPMCSR.

Issue an LPM instruction within three clock cycles.

Read the lock bits from the LPM destination register.

If successful, the contents of the destination register are as follows.

See section “Program And Data Memory Lock Bits” on page 168 for more information.

17.6.2

Reading Fuse Bits from Firmware

The algorithm for reading fuse bytes is similar to the one described above for reading lock bits,

only the addresses are different. To read the Fuse Low Byte (FLB), follow the below procedure:

Load the Z-pointer with 0x0000.

Set RFLB and SELFPRGEN bits in SPMCSR.

Issue an LPM instruction within three clock cycles.

Read the FLB from the LPM destination register.

If successful, the contents of the destination register are as follows.

Refer to Table 18-5 on page 170 for a detailed description and mapping of the Fuse Low Byte.

Bit

654321

–

–––––

LB2

LB1

Bit

543

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

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